[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Fill FSPM UPDs for VT-d configuration

[Meera Ravindranath (Code Review)]

Attention is currently required from:  Felix Singer, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Ronak Kanabar, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 )

Change subject: soc/intel/alderlake: Fill FSPM UPDs for VT-d configuration
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Patch Set 12:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51849/comment/08c74fd0_34f9389a 
PS11, Line 7: Enable VT-d
> The code gives the opportunity for VT-d configuration. Rather write something like: […]

Done

https://review.coreboot.org/c/coreboot/+/51849/comment/96916a14_b7597030 
PS11, Line 9: enabling
> configuring

Done

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/51849/comment/c85fd8c7_00d812ec 
PS11, Line 230:
> What about TBT0BAR, etc. […]

Currently we only need VtdBaseAddress 0,1 and 2 and not using beyond that. Confirmed from the FSP code.