Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31968
Change subject: mediatek/mt8183: Fix RTC initialization flow ......................................................................
mediatek/mt8183: Fix RTC initialization flow
1. fix RTC initialization flow 2. fix RTC lpd settings
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Signed-off-by: Ran Bi ran.bi@mediatek.com --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8173/include/soc/rtc.h M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 6 files changed, 77 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31968/1
diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 41e772e..b652ad5 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -99,7 +99,6 @@ int rtc_writeif_unlock(void); void rtc_xosc_write(u16 val); int rtc_reg_init(void); -u8 rtc_check_state(void); void rtc_boot_common(void);
#endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fd40cb5..647ae1e 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -137,7 +137,7 @@ return rtc_write_trigger(); }
-u8 rtc_check_state(void) +static u8 rtc_check_state(void) { u16 con; u16 pwrky1; @@ -147,6 +147,9 @@ pwrap_read(RTC_POWERKEY1, &pwrky1); pwrap_read(RTC_POWERKEY2, &pwrky2);
+ printk(BIOS_INFO, "[RTC] con = %x, pwrkey1 = %x, pwrkey2 = %x\n", + con, pwrky1, pwrky2); + if (con & RTC_CON_LPSTA_RAW) return RTC_STATE_INIT;
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index fe5cbac..0ee944a 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -112,7 +112,7 @@
/* external API */ void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void);
#endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 5b7d486..056c051 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -71,15 +71,15 @@ }
/* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
if (!rtc_writeif_unlock()) - return 0; + return false;
if (!rtc_gpio_init()) - return 0; + return false;
/* Use SW to detect 32K mode instead of HW */ if (recover) @@ -94,7 +94,7 @@ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false;
if (recover) pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9); @@ -102,11 +102,11 @@ rtc_xosc_write(0);
if (!rtc_reg_init()) - return 0; + return false; if (!rtc_lpd_init()) - return 0; + return false;
- return 1; + return true; }
/* enable rtc bbpu */ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 08ebe98..b0c1d4a 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -106,6 +106,14 @@ RTC_REG_XOSC32_ENB = 1 << 15 };
+enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, + RTC_LPD_OPT_EOSC_LPD = 1 << 13, + RTC_LPD_OPT_XOSC_LPD = 2 << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, + RTC_LPD_OPT_MASK = 3 << 13 +}; + /* PMIC TOP Register Definition */ enum { PMIC_RG_SCK_TOP_CON0 = 0x050C @@ -142,7 +150,7 @@ /* external API */ void rtc_bbpu_power_on(void); void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void);
#endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index d67315b..69e4f0c 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -64,7 +64,8 @@
/* Export 32K clock RTC_32K2V8 */ pwrap_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); con |= (RTC_CON_GPEN | RTC_CON_GOE); con &= ~(RTC_CON_F32KOB); pwrap_write(RTC_CON, con); @@ -81,9 +82,17 @@ /* low power detect setting */ static int rtc_lpd_init(void) { - u16 con; + u16 con, sec;
- con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN; + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + + pwrap_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -99,7 +108,8 @@ if (!rtc_write_trigger()) return 0;
- con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN; + pwrap_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -115,6 +125,18 @@ if (!rtc_write_trigger()) return 0;
+ pwrap_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + pwrap_write(RTC_CON, con); + + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + return 1; }
@@ -142,36 +164,46 @@ }
/* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
- if (!rtc_writeif_unlock()) - return 0; - - if (!rtc_gpio_init()) - return 0; - - /* using dcxo 32K clock */ - rtc_enable_dcxo(); - - if (recover) - mdelay(20); - /* write powerkeys */ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false; + + if (!rtc_writeif_unlock()) + return false; + + /* using dcxo 32K clock */ + rtc_enable_dcxo(); + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) + return false; + + if (!rtc_hw_init()) + return false;
if (!rtc_reg_init()) - return 0; - if (!rtc_lpd_init()) - return 0; - if (!rtc_hw_init()) - return 0; + return false;
- return 1; + if (!rtc_lpd_init()) + return false; + + /* write powerkeys again to enable lpd */ + pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!rtc_write_trigger()) + return false; + + if (!rtc_writeif_unlock()) + return false; + + return true; }
/* enable rtc bbpu */