Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47045 )
Change subject: soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write ......................................................................
soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write
This is what Lynxpoint does. It is equivalent, but simpler.
Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/lpc.c 1 file changed, 9 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 4cb1620..84b8d00 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -156,6 +156,15 @@ default: state = "undefined"; } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state);
@@ -174,21 +183,8 @@ static void pch_misc_init(struct device *dev) { u8 reg8; - u16 reg16; u32 reg32;
- reg16 = pci_read_config16(dev, GEN_PMCON_3); - - reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ - - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - - pci_write_config16(dev, GEN_PMCON_3, reg16); - /* Prepare sleep mode */ reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); reg32 &= ~SLP_TYP;