Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32326
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
BUG=b:129707481 BRANCH=none TEST=Compiles.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c A src/mainboard/google/hatch/variants/kohaku/gpio.c 2 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 0391dfe..784dd6c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -232,7 +232,7 @@
/* E0 : GPP_E0 ==> NC */ PAD_NC(GPP_E0, NONE), - /* E1 : SATAPCIE1 */ + /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E2 : GPP_E2 ==> NC */ PAD_NC(GPP_E2, NONE), diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c new file mode 100644 index 0000000..c7d7213 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), + /* SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* PIRQA# ==> NC */ + PAD_NC(GPP_A17, NONE), + /* ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* SRCCLKREQ3#: NC */ + PAD_NC(GPP_B8, NONE), + /* SMBDATA: NC */ + PAD_NC(GPP_C1, NONE), + /* + * Hoping that GPP_A8 can be used for both interrupt (SCI) and wake + * (GPIO). Keeping as GPI for now, but with the option to change later. + */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), + /* EN_PP3300_TSP_DIG_DX */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + /* GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIO settings before entering S5 + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} +