Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smbus_spd.c 4 files changed, 24 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/1
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c3a4d41..f6cba68 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,6 +17,7 @@ #define _HUDSON_EARLY_SETUP_C_
#include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -74,11 +75,7 @@ pci_devfn_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 8eb36f4..a63f5e6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> @@ -126,16 +127,10 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 34a3513..6e47e42 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,6 +18,7 @@
#include <assert.h> #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -36,18 +37,17 @@ { u8 byte;
- byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16))); + byte = aoac_read8(FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); - byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), + byte); + + aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); + iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ + iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ + iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ + iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */
udelay(2000); write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), @@ -107,11 +107,7 @@ pci_devfn_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); @@ -236,8 +232,7 @@ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); + biosram_write8(nvram_pos, (dword >> (8 * i)) & 0xff); nvram_pos++; }
@@ -249,9 +244,8 @@ u32 data = *old_dword; int i; for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); + data |= biosram_read8(nvram_pos) << (i *8); nvram_pos++; } *old_dword = data; @@ -268,11 +262,11 @@ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + ctrl = misc_read32(FCH_MISC_REG40);
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ ctrl &= (u32)~(1<<2); - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); + misc_write32(FCH_MISC_REG40, ctrl); }
static uintptr_t hudson_spibase(void) diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index c49ccff..c046c28 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/pci_def.h> #include <device/device.h> @@ -127,16 +128,10 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }