[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd: Reserve PCIe MMCONF in ACPI

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74807 )

Change subject: soc/amd: Reserve PCIe MMCONF in ACPI
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Patch Set 2: -Code-Review

(1 comment)

Patchset:

PS2:
> i tested on both mandolin (picasso) and careena (stoneyridge). […]

hm, not sure if the change in /proc/iomem is an improvement.

on mandolin it was before

f8000000-fbffffff : PCI MMCONFIG 0000 [bus 00-3f]
  f8000000-fbffffff : Reserved

and is now

f8000000-fbffffff : PCI MMCONFIG 0000 [bus 00-3f]
  f8000000-fbffffff : Reserved
    f8000000-fbffffff : PCI Bus 0000:00

there's also

d0000000-f7ffffff : PCI Bus 0000:00

so i'd guess that the PCI Bus means PCI MMIO and not MMCONF?!

the vendor UEFI firmware on some laptop with AMD APU returns the MMCONF region as DWordMemory from the PCI0 _CRS method; it uses DWordMemory instead of Memory32Fixed everywhere though, so DWordMemory vs Memory32Fixed likely isn't the issue