Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21053
Change subject: intel/cannonlake/chip: Add initial PCI enum support ......................................................................
intel/cannonlake/chip: Add initial PCI enum support
Add callbacks for initial PCI devices enumeration.
Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668 Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com --- M src/soc/intel/cannonlake/chip.c 1 file changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21053/1
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2f893e3..62181a3 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -15,8 +15,8 @@
#include <chip.h> #include <console/console.h> +#include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <fsp/api.h> #include <fsp/util.h> #include <romstage_handoff.h> @@ -29,8 +29,37 @@ fsp_silicon_init(romstage_handoff_is_resume()); }
+static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; +} + struct chip_operations soc_intel_cannonlake_ops = { CHIP_NAME("Intel Cannonlake") + .enable_dev = &soc_enable, .init = &soc_init_pre_device, };