[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 )

Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/early_tcss.h:

https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/inc... 
PS1, Line 103: 0x09000000
> for the GPIO pins this is how FSP has them defined and what it is expecting. see FspsUpd. […]

I see, it's a chipset-specific constant, thanks Brandon!
Caveh, how about a `#define TGL_LP_GPIO_ID 0x09000000` instead?