[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move GPIO PM configuration to soc level

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )

Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
File src/soc/intel/cannonlake/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
PS5, Line 79: /* Enable GPIO PM */
            : 				_SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
> I like that idea as well, then no need to have NVS

@Furquan
> > During runtime S0ix, software is not aware of it and hence neither LPIT DSM nor _PTS/_WAK are called

I guess Kane told that _DSM is getting called