Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsuportted - update soc_intel_tigerlake_config struct
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/1
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 530893c..44e1e51 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,6 +34,38 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0";
+ if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; +} if (dev->path.type != DEVICE_PATH_PCI) return NULL;
@@ -43,20 +75,20 @@ case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_I2C6: return "I2C6"; + case PCH_DEVFN_I2C7: return "I2C7"; case PCH_DEVFN_CSE: return "CSE1"; case PCH_DEVFN_CSE_2: return "CSE2"; case PCH_DEVFN_CSE_IDER: return "CSED"; case PCH_DEVFN_CSE_KT: return "CSKT"; case PCH_DEVFN_CSE_3: return "CSE3"; case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -73,21 +105,20 @@ case PCH_DEVFN_PCIE14: return "RP14"; case PCH_DEVFN_PCIE15: return "RP15"; case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_UART3: return "UAR3"; + case PCH_DEVFN_UART4: return "UAR4"; + case PCH_DEVFN_UART5: return "UAR5"; + case PCH_DEVFN_UART6: return "UAR6"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_GSPI3: return "SPI3"; + case PCH_DEVFN_GSPI4: return "SPI4"; + case PCH_DEVFN_GSPI5: return "SPI5"; + case PCH_DEVFN_GSPI6: return "SPI6"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; @@ -103,22 +134,6 @@ } #endif
-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ -static void soc_fill_gpio_pm_configuration(void) -{ - uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - else - memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - - gpio_pm_configure(value, TOTAL_GPIO_COMM); -} - void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -133,8 +148,6 @@
/* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - soc_fill_gpio_pm_configuration(); }
static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5e0fcd1..7131203 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -96,7 +96,6 @@ SaGv_Enabled, } SaGv;
- /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT;
@@ -116,22 +115,6 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8];
- /* Audio related */ - uint8_t PchHdaEnable; - uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; - /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to Pcie devices. @@ -145,23 +128,6 @@ /* SMBus */ uint8_t SmbusEnable;
- /* eMMC and SD */ - uint8_t ScsEmmcHs400Enabled; - /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcUseCustomDlls; - uint32_t EmmcTxCmdDelayRegValue; - uint32_t EmmcTxDataDelay1RegValue; - uint32_t EmmcTxDataDelay2RegValue; - uint32_t EmmcRxCmdDataDelay1RegValue; - uint32_t EmmcRxCmdDataDelay2RegValue; - uint32_t EmmcRxStrobeDelayRegValue; - - /* Enable if SD Card Power Enable Signal is Active High */ - uint8_t SdCardPowerEnableActiveHigh; - - /* Integrated Sensor */ - uint8_t PchIshEnable; - /* Heci related */ uint8_t Heci3Enabled;
@@ -198,11 +164,17 @@ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
+ /* Statically clock gate 8254 PIT. */ + uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; - + /* + * PRMRR size setting with below options + * 0x00100000 - 1MiB + * 0x02000000 - 32MiB and beyond + */ + uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ enum { DebugConsent_Disabled, @@ -248,25 +220,6 @@ FORCE_ENABLE, FORCE_DISABLE, } CnviBtAudioOffload; - - /* - * Override GPIO PM configuration: - * 0: Use FSP default GPIO PM program, - * 1: coreboot to override GPIO PM program - */ - uint8_t gpio_override_pm; - - /* - * GPIO PM configuration: 0 to disable, 1 to enable power gating - * Bit 6-7: Reserved - * Bit 5: MISCCFG_GPSIDEDPCGEN - * Bit 4: MISCCFG_GPRCOMPCDLCGEN - * Bit 3: MISCCFG_GPRTCDLCGEN - * Bit 2: MISCCFG_GSXLCGEN - * Bit 1: MISCCFG_GPDPCGEN - * Bit 0: MISCCFG_GPDLCGEN - */ - uint8_t gpio_pm[TOTAL_GPIO_COMM]; };
typedef struct soc_intel_tigerlake_config config_t;