Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64038 )
Change subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF ......................................................................
soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
We encountered a delay issue when powering down. The root cause is the incorrect setting for delay time.
The meaning of PMIC_CPSDSA4[4:0] is: power down at specified time slot. If PMIC_CPSDSA4[4:0] is 0xA, in this time slot, it cause delay 20ms comparing with 0xF.
To resolve this issue, we need to change to correct time slot. Therefore, we change the value from 0xA to 0xF.
This modification is based on chapter 3.7 in the MT8186 functional specification.
BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct.
Signed-off-by: zhiyong tao zhiyong.tao@mediatek.corp-partner.google.com Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/64038/1
diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 8dd2997..af5403a 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -807,8 +807,8 @@ static void wk_power_down_seq(void) { mt6366_protect_control(false); - /* Set VPROC12 sequence to VA12 */ - pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0); + /* Set VPROC12 power-down time slot to 0xF to avoid 20ms delay */ + pwrap_write_field(PMIC_CPSDSA4, 0xF, 0x1F, 0); mt6366_protect_control(true); }