Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10988
-gerrit
commit 664847745511dda4f905a0263b3991792fe0a3d4 Author: Naveen Krishna Chatradhi naveenkrishna.ch@intel.com Date: Mon Jul 6 16:42:56 2015 +0530
Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol
This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe.
BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled"
Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi naveenkrishna.ch@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Tested-by: Wenkai Du wenkai.du@intel.com --- src/mainboard/intel/sklrvp/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 4c764c0..22ce473 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE select INTEL_PCH_UART_CONSOLE select SOC_INTEL_SKYLAKE select VBOOT_DYNAMIC_WORK_BUFFER