[coreboot-gerrit] Change in coreboot[master]: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47038 )

Change subject: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47038/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47038/2//COMMIT_MSG@9 
PS2, Line 9: For all these southbridges, the lower nibble of PCICMD is read-only.
And for newer chips, the special bit is even supposed to be 0...

Anyway, was this tested? Sometimes datasheets can be deceiving and read-
only actually means read-only to the OS.