Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52745 )
Change subject: device/dram: Add support for LPDDR4 4266 ......................................................................
device/dram: Add support for LPDDR4 4266
Add 4266 MT/s LPDDD4 to a separate lpddr4_speed table. Set min/max limits to 1866/2133 MHz per JEDEC 209-4C.
BUG=b:184124605
Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Signed-off-by: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com --- M src/device/dram/ddr4.c 1 file changed, 42 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/52745/1
diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index cc66dcc..932845c 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -19,6 +19,10 @@ DDR4_3200 };
+enum lpddr4_speed_grade { + LPDDR4_4266 +}; + struct ddr4_speed_attr { uint32_t min_clock_mhz; // inclusive uint32_t max_clock_mhz; // inclusive @@ -72,6 +76,17 @@ } };
+/** + * LPDDR4 speed attributes derived from JEDEC 209-4C tables 95 & 96 + */ +static const struct ddr4_speed_attr lpddr4_speeds[] = { + [LPDDR4_4266] = { + .min_clock_mhz = 1866, + .max_clock_mhz = 2133, + .reported_mts = 4266 + } +}; + typedef enum { BLOCK_0, /* Base Configuration and DRAM Parameters */ BLOCK_1, @@ -132,18 +147,40 @@ }
/** - * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + * Finds matching speed grade table entry in MT/s for supplied clock speed in MHz */ -uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +static uint16_t speed_mhz_to_reported_mts(uint16_t speed_mhz, + const struct ddr4_speed_attr *speed_table, uint16_t table_size) { - for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) { - const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed]; + for (uint16_t speed = 0; speed < table_size; speed++) { + const struct ddr4_speed_attr *speed_attr = &speed_table[speed]; if (speed_mhz >= speed_attr->min_clock_mhz && speed_mhz <= speed_attr->max_clock_mhz) { return speed_attr->reported_mts; } } - printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range", speed_mhz); + /* no matching speed found */ + return 0; +} + +/** + * Converts DDR4/LPDD4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +{ + uint16_t mts; + + /* check for matching DDR4 speed first */ + mts = speed_mhz_to_reported_mts(speed_mhz, ddr4_speeds, sizeof(ddr4_speeds)); + if (mts) + return mts; + + /* check for matching LPDDR4 speed next */ + mts = speed_mhz_to_reported_mts(speed_mhz, lpddr4_speeds, sizeof(lpddr4_speeds)); + if (mts) + return mts; + + printk(BIOS_ERR, "ERROR: DDR4/LPDDR4 speed of %d MHz is out of range", speed_mhz); return 0; }