[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Program GPIO for M.2 PCH SSD

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46417 )

Change subject: mb/intel/adlrvp: Program GPIO for M.2 PCH SSD
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mb/intel/adlrvp: Program GPIO for M.2 PCH SSD

This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port
Detect (GPP_A12) as per schematics.

TEST=Able to build and boot ADL RVP.

Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46417/1

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
index 5a21992..e142e88 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
@@ -70,7 +70,11 @@
    PAD_CFG_GPO(GPP_H1, 1, PLTRST),
    /* Sata direct Power */
    PAD_CFG_GPO(GPP_B4, 1, PLTRST),
+	/* M.2_PCH_SSD_PWREN */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),

+	/* M.2_SSD_PDET_R */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
    /* THC0 SPI1 CLK */
    PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
    /* THC0 SPI1 IO 1 */