Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39865 )
Change subject: soc/intel/tigerlake: Reorganize memory initialization support
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Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39865/2/src/soc/intel/tigerlake/mem...
File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39865/2/src/soc/intel/tigerlake/mem...
PS2, Line 40: Reserved9
I can't see this. […]
Unfortunately, this is currently only visible to Intel. It is primarily a request to Intel to open up the UPDs.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Gerrit-Change-Number: 39865
Gerrit-PatchSet: 3
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