[coreboot-gerrit] [L] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code

[Felix Singer (Code Review)]

Attention is currently required from: Jonathan Zhang.

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72443 )

Change subject: soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code
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Patch Set 13:

(1 comment)

File src/soc/intel/xeon_sp/spr/cpu.c:

https://review.coreboot.org/c/coreboot/+/72443/comment/6d685892_536959b8 
PS13, Line 177: static const struct cpu_device_id cpu_table[] = {
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_D},
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E0},
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E2},
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E3},
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E4},
              : 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_Ex},
              : 	{0, 0},
              : };
> Good catch, thanks for helping on this Felix :)

Fix got submitted. Done.