[coreboot-gerrit] Change in coreboot[master]: drivers/intel/fsp2_0: Use coreboot postcar with FSP-T

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Jonathan Zhang, Christian Walter, Angel Pons, Subrata Banik, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48466

to look at the new patch set (#2).

Change subject: drivers/intel/fsp2_0: Use coreboot postcar with FSP-T
......................................................................

drivers/intel/fsp2_0: Use coreboot postcar with FSP-T

Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.

There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
  overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
  causes problems with cbfs_mcache)

Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans 
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
M src/soc/intel/common/block/cpu/Makefile.inc
3 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48466/2