Jonathan A. Kollasch (jakllsch@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3963
-gerrit
commit 07e8b2656b943f9c56825c4ad77f1a832f3c90fb Author: Jonathan A. Kollasch jakllsch@kollasch.net Date: Fri Oct 11 16:14:18 2013 -0500
ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000. This causes IOAPIC interrupts to fail to work under Linux. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked.
Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- src/southbridge/nvidia/ck804/lpc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 4b33a3c..d52d1e7 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -53,15 +53,10 @@
static void lpc_common_init(device_t dev) { - u8 byte; u32 dword; struct resource *res;
/* I/O APIC initialization. */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable APIC. */ - pci_write_config8(dev, 0x74, byte); - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ @@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev)
static void ck804_lpc_set_resources(device_t dev) { + u8 byte; struct resource *res;
pci_dev_set_resources(dev); @@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev) /* APIC */ res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { + byte = pci_read_config8(dev, 0x74); + byte |= (1 << 1); /* enables access to PCI_BASE_ADDRESS_1 */ + byte |= (1 << 0); /* enables decode of IOAPIC space */ + pci_write_config8(dev, 0x74, byte); pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); + byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); }
/* HPET */