Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71715 )
Change subject: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree ......................................................................
soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0.
Remove the incorrect comment and make the UPD configurable from the devicetree.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 26 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index cea63bf..04a4a22 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -348,6 +348,7 @@ uint16_t sata_ports_dito_val[8];
/* Audio related */ + uint8_t pch_hda_audio_link_hda_enable; uint8_t pch_hda_dsp_enable;
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 6016bff..f18e1f4 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -242,13 +242,7 @@ m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; - /* - * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to - * configure GPIO pads for audio. Mainboard is expected to perform all GPIO - * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO - * configuration for audio pads. - */ - m_cfg->PchHdaAudioLinkHdaEnable = 0; + m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable; memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));