Duncan Laurie (dlaurie@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17134
-gerrit
commit 9a3ca308b78a8fd3817b509671150c572fdbf05f Author: Duncan Laurie dlaurie@chromium.org Date: Tue Oct 25 19:58:27 2016 -0700
skylake: Add support for eSPI SMI events
Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC.
BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system.
Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/include/soc/pm.h | 1 + src/soc/intel/skylake/include/soc/smm.h | 2 ++ src/soc/intel/skylake/pmutil.c | 3 ++- src/soc/intel/skylake/smi.c | 3 ++- src/soc/intel/skylake/smihandler.c | 7 +++++++ 5 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 235ad89..91f037a 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -46,6 +46,7 @@ #define SMI_EN 0x30 #define XHCI_SMI_EN (1 << 31) #define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) #define GPIO_UNLOCK_SMI_EN (1 << 27) #define INTEL_USB2_EN (1 << 18) #define LEGACY_USB2_EN (1 << 17) diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 1beaaa4..71083b3 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -50,6 +50,8 @@ struct smm_relocation_params { /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts);
+/* Mainboard handler for eSPI SMIs */ +void mainboard_smi_espi_handler(void);
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 31de242..e450ce8 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -173,7 +173,8 @@ static u32 print_smi_status(u32 smi_sts) [20] = "PCI_EXP_SMI", [21] = "MONITOR", [26] = "SPI", - [27] = "GPIO_UNLOCK" + [27] = "GPIO_UNLOCK", + [28] = "ESPI_SMI", };
if (!smi_sts) diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c index 77f3951..442607f 100644 --- a/src/soc/intel/skylake/smi.c +++ b/src/soc/intel/skylake/smi.c @@ -62,11 +62,12 @@ void southbridge_smm_enable_smi(void) * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS); }
void southbridge_trigger_smi(void) diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 1834815..872cce1 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -361,6 +361,12 @@ static void southbridge_smi_gpi(void) gpi_clear_get_smi_status(&smi_sts); }
+void __attribute__((weak)) mainboard_smi_espi_handler(void) { } +static void southbridge_smi_espi(void) +{ + mainboard_smi_espi_handler(); +} + static void southbridge_smi_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -482,6 +488,7 @@ static smi_handler_t southbridge_smi[SMI_STS_BITS] = { [PM1_STS_BIT] = southbridge_smi_pm1, [GPE0_STS_BIT] = southbridge_smi_gpe0, [GPIO_STS_BIT] = southbridge_smi_gpi, + [ESPI_SMI_STS_BIT] = southbridge_smi_espi, [MCSMI_STS_BIT] = southbridge_smi_mc, [TCO_STS_BIT] = southbridge_smi_tco, [PERIODIC_STS_BIT] = southbridge_smi_periodic,