Duncan Laurie (dlaurie@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17776
-gerrit
commit c39fafa63941ebf6f2a4804f1446b9fca7eeae8f Author: Duncan Laurie dlaurie@chromium.org Date: Thu Dec 8 10:48:06 2016 -0800
google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/mainboard/google/eve/acpi/mainboard.asl | 40 +++++++++++++++++++++++++++++ src/mainboard/google/eve/dsdt.asl | 3 +++ 2 files changed, 43 insertions(+)
diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl new file mode 100644 index 0000000..55a99b6 --- /dev/null +++ b/src/mainboard/google/eve/acpi/mainboard.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.SPI1) +{ + Device (FPC) + { + Name (_HID, "FPC1020") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + SpiSerialBus ( + 0, // DeviceSelection (CS0) + PolarityLow, // DeviceSelectionPolarity + FourWireMode, // WireMode + 8, // DataBitLength + ControllerInitiated, // SlaveMode + 1000000, // ConnectionSpeed (1MHz) + ClockPolarityLow, // ClockPolarity + ClockPhaseFirst, // ClockPhase + "\_SB.PCI0.SPI1", // ResourceSource + 0, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 } + }) + } +} diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 2882d50..22b92f3 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -67,4 +67,7 @@ DefinitionBlock( { #include "acpi/dptf.asl" } + + /* ACPI code for EC functions */ + #include "acpi/mainboard.asl" }