[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add SPI speed devicetree settings and EM100 support

[Felix Held (Code Review)]

Hello Rob Barnes,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40421

to review the following change.

Change subject: soc/amd/picasso: Add SPI speed devicetree settings and EM100 support
......................................................................

soc/amd/picasso: Add SPI speed devicetree settings and EM100 support

The EM100 SPI flash emulator has a limited SPI frequency support, so
ignore higher frequency setting in the devicetree in the case that EM100
usage is selected in Kconfig.

BUG=b:147758054
BUG=b:153675510

Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Rob Barnes 
Signed-off-by: Felix Held 
Reviewed-on: https://chromium-review.googlesource.com/2045134
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/southbridge.c
3 files changed, 33 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40421/1

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index d9211b4..b5e9c25 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -32,6 +32,7 @@
    select GENERIC_GPIO_LIB
    select IOAPIC
    select HAVE_USBDEBUG_OPTIONS
+	select HAVE_EM100_SUPPORT
    select TSC_MONOTONIC_TIMER
    select SOC_AMD_COMMON_BLOCK_SPI
    select TSC_SYNC_LFENCE
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 53c0329..90d0af5 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -9,6 +9,7 @@
 #include <commonlib/helpers.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/i2c.h>
+#include <soc/southbridge.h>
 #include <arch/acpi_device.h>

#define PICASSO_I2C_DEV_MAX 4
@@ -32,6 +33,14 @@
    	I2S_PINS_I2S_TDM = 4,
    	I2S_PINS_UNCONF = 7,	/* All pads will be input mode */
    } acp_pin_cfg;
+
+	/* SPI Config */
+	bool spi_override_defaults;
+	uint32_t spi_normal_speed;
+	uint32_t spi_fast_speed;
+	uint32_t spi_altio_speed;
+	uint32_t spi_tpm_speed;
+	uint32_t spi_read_mode;
 };

typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 6bedab0..4c463ad 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -238,6 +238,28 @@
    				& ~SPI_READ_MODE_MASK) | mode);
 }

+static void sb_spi_init(void)
+{
+	lpc_enable_spi_prefetch();
+	sb_init_spi_base();
+	sb_disable_4dw_burst();
+
+	const config_t *config = config_of_soc();
+	if(!CONFIG(EM100) && config != NULL && config->spi_override_defaults) {
+		sb_read_mode(config->spi_read_mode);
+		sb_set_spi100(config->spi_normal_speed,
+				config->spi_fast_speed,
+				config->spi_altio_speed,
+				config->spi_tpm_speed);
+	} else {
+		sb_read_mode(SPI_READ_MODE_NOM);
+		sb_set_spi100(SPI_SPEED_16M,	/* Normal */
+				SPI_SPEED_16M,	/* Fast   */
+				SPI_SPEED_16M,	/* AltIO  */
+				SPI_SPEED_16M);	/* TPM    */
+	}
+}
+
 static void fch_smbus_init(void)
 {
    /* 400 kHz smbus speed. */
@@ -263,11 +285,7 @@
    if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
    				&& CONFIG(PICASSO_LPC_IOMUX))
    	lpc_enable_port80();
-	lpc_enable_spi_prefetch();
-	sb_init_spi_base();
-	sb_disable_4dw_burst();
-	sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M,
-			SPI_SPEED_16M, SPI_SPEED_16M);
+	sb_spi_init();
    enable_acpimmio_decode_pm04();
    fch_smbus_init();
    sb_enable_cf9_io();