Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/34906c70_20aa02d2
PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Maybe not running with specific speed/frequency?
@Subrata, what we want to figure out is if CLKSRC is free running still bond to RP and CLKREQ no matter use mux or not. At least, when I developed NB in windows, there always have CLKREQ bond to the CLKSRC or the LAN would not work.
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