Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35204 )
Change subject: [TEST-ONLY] Distinguish SKU1 and 2 for eMMC and SSD respectively ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 4: I need clarify interrupt is one of side effects. As I know 1. correct SKU ID must point to correct GPIO configuration, if not, will lead to side effects include interrupt storm. 2. Why will impact S0ix if don't close these relevant GPIOs. As I know if no device attach to the platform, relevant device can't respond system request when enter S0ix, so block system enter S0ix. for example PCI-E device need enable ASPM(L1.1 or L1.2) and if no relevant PCI-E device on platform, which will block system enter S0ix. 3. as I know if controller are disabled, need close relevant GPIOs(generally configure IO is GPI and Hi-Z), If not, these GPIOs may be impacted by external electromagnetic environment.
Whether eMMC or SSD in M/B will be locked down during SMT by BOM therefore could we take care of that for non-mounting one (either eMMC or SSD) we can fine-tune pins for N/C, PU or PD to avoid any leakage or interrupt storm? As a result, at least we can support 255?
Dear Marco, sorry feedback to you later. I confirmed with our factory team and PM, Proto board just power on, BTW don't do factory flow. So I think SKU255 for Proto build that is fine.