Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri
According to FSP code, the UPD is interface for writing value in IOM_TYPEC_SW_CONFIGURATION_3 accord […]
My point is why does coreboot not write to this register directly instead of setting the UPD?
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));
We already check if it's possible like Image clock or ISH pins but it's not only for pin mux. […]
Same question as before. Even if there are multiple options, can't those be configured in coreboot? Also, if there are IOM registers that need to be set, coreboot should be able to do it. I don't agree with the setting of magic values as pad cfgs in UPDs to make FSP do the work which coreboot can do itself.