Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer.
Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )
Change subject: mb/google/myst: Enable PCIe devices in devicetree ......................................................................
Patch Set 31:
(5 comments)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/3fa30a4b_4d7d2c85 PS31, Line 12: .start_logical_lane = 13, : .end_logical_lane = 13,
The actual schematic shows lane 13, not sure why the block diagram shows lane 12. I'll follow up with EE's.
https://ee-schematics.teams.x20web.corp.google.com/myst/myst/proto0/referenc...
https://review.coreboot.org/c/coreboot/+/74112/comment/29d71499_eeddd34a PS31, Line 18: .link_aspm = ASPM_L1, : .link_aspm_L1_1 = true, : .link_aspm_L1_2 = true,
Considering all of the trouble we've had with ASPM in the past, I would suggest disabling it for all […]
Done
https://review.coreboot.org/c/coreboot/+/74112/comment/16668d6d_f79ad915 PS31, Line 44: GEN3
GEN1
Done
https://review.coreboot.org/c/coreboot/+/74112/comment/5b04655e_c1ae8e43 PS31, Line 59: GEN3
GEN4
Done
https://review.coreboot.org/c/coreboot/+/74112/comment/017011b0_97c019bd PS31, Line 101: *dxio_descs = myst_phx_dxio_descriptors; : *dxio_num = ARRAY_SIZE(myst_phx_dxio_descriptors); : *ddi_descs = myst_phx_ddi_descriptors; : *ddi_num = ARRAY_SIZE(myst_phx_ddi_descriptors);
I would expect them to keep working, but I think it's possible that there would be a delta. […]
Done