[coreboot-gerrit] Change in coreboot[master]: sc7280: DDR One-Time-Training Support

[Ravi kumar (Code Review)]

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54352 )

Change subject: sc7280: DDR One-Time-Training Support
......................................................................

sc7280: DDR One-Time-Training Support

Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi 
---
M src/mainboard/google/herobrine/chromeos.fmd
M src/soc/qualcomm/sc7280/memlayout.ld
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54352/1

diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd
index a44a638..e85271c 100644
--- a/src/mainboard/google/herobrine/chromeos.fmd
+++ b/src/mainboard/google/herobrine/chromeos.fmd
@@ -17,7 +17,7 @@

RW_VPD(PRESERVE) 32K
    RW_NVRAM(PRESERVE) 16K
-	RW_DDR_TRAINING(PRESERVE) 8K
+	RW_MRC_CACHE(PRESERVE) 32K
    RW_LIMITS_CFG(PRESERVE) 4K
    RW_ELOG(PRESERVE) 4K
    RW_SHARED 4K {
diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld
index 121fd93..84c5a96 100644
--- a/src/soc/qualcomm/sc7280/memlayout.ld
+++ b/src/soc/qualcomm/sc7280/memlayout.ld
@@ -40,14 +40,14 @@
    STACK(0x1484B000, 16K)
    VBOOT2_WORK(0x1484F000, 12K)
    DMA_COHERENT(0x14853000, 8K)
-	REGION(ddr_training, 0x14855000, 8K, 4K)
    REGION(qclib_serial_log, 0x14857000, 4K, 4K)
    REGION(ddr_information, 0x1485B000, 1K, 1K)
    FMAP_CACHE(0x1485B400, 2K)
    CBFS_MCACHE(0x1485BC00,8K)
    REGION(dcb, 0x1485E000, 32K, 4K)
    REGION(pmic, 0x14866000, 96K, 4K)
-	REGION(qclib, 0x1487E000, 840K, 4K)
+	REGION(ddr_training, 0x1487E000, 32K, 4K)
+	REGION(qclib, 0x14886000, 800K, 4K)
    BSRAM_END(0x14950000)

DRAM_START(0x80000000)