Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43408 )
Change subject: [WIP] mb/google/zork: add dptc support ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43408/3/src/ec/google/chromeec/acpi... File src/ec/google/chromeec/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43408/3/src/ec/google/chromeec/acpi... PS3, Line 364: _SB.DPTC(0x0) Why is this done here?
https://review.coreboot.org/c/coreboot/+/43408/3/src/ec/google/chromeec/acpi... PS3, Line 386: 0x1 Is the argument 0x1 meant to indicate tablet mode is enabled? If so, then this is not correct. Host event 29 indicates mode change - it could be either tablet mode entry or tablet mode exit(or some other mode change). You will have to check _SB.PCI0.LPCB.EC0.RCDP() in _SB.DPTC() to decide whether tablet mode is entered or exited.