Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26707
Change subject: cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE ......................................................................
cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE
Change-Id: Ieeaee7b47fc9c31e9abae8c49e16f62bee7c76d5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/cache_as_ram_ht.inc 1 file changed, 2 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26707/1
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 58dbf29..7fc92fc 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -334,18 +334,13 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $(-CACHE_ROM_SIZE), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr
post_code(0x2e)