[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

[Jamie Ryu (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Angel Pons, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42790

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
......................................................................

soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.

BUG=b:159884143
TEST=build and boot volteer with serial and non-serial image

Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42790/5