[coreboot-gerrit] Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47350 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A

BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x &&
./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \
global_lp4x_mem_parts.json.txt "TGL"

Signed-off-by: David Wu 
Change-Id: I37702770f707fe078920694468552c5db59c478f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350
Reviewed-by: Nick Vaccaro 
Reviewed-by: Paul Fagerburg 
Reviewed-by: Caveh Jalali 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
2 files changed, 39 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Caveh Jalali: Looks good to me, but someone else must approve
  Paul Fagerburg: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
index 70877d2..c7e9690 100644
--- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
@@ -13,3 +13,6 @@
 K4UBE3D4AA-MGCR,lp4x-spd-3.hex
 MT53E512M64D4NW-046 WT:E,lp4x-spd-1.hex
 MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex
+H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex
+H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex
+MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex
diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 109fadb..91062d0 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -181,6 +181,42 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 4267
             }
+        },
+        {
+            "name": "H9HCNNNCRMBLPR-NEE",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "H9HCNNNFBMBLPR-NEE",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "MT53D1G64D4NW-046 WT:A",
+            "attribs": {
+                "densityPerChannelGb": 16,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
         }
     ]
 }