Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36137 )
Change subject: soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to common code ......................................................................
soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to common code
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code.
Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/ebda/ebda.c M src/soc/intel/common/block/include/intelblocks/ebda.h A src/soc/intel/common/block/memmap/Kconfig A src/soc/intel/common/block/memmap/Makefile.inc R src/soc/intel/common/block/memmap/memmap.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/Makefile.inc 11 files changed, 26 insertions(+), 323 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36137/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141..1588bde 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock/report_platform.c bootblock-y += gspi.c bootblock-y += i2c.c -bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += p2sb.c @@ -26,7 +25,6 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += lpc.c -romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -44,7 +42,6 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c ramstage-y += pmc.c @@ -66,7 +63,6 @@ smm-y += uart.c smm-y += xhci.c
-postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c deleted file mode 100644 index 4973e8d..0000000 --- a/src/soc/intel/cannonlake/memmap.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <fsp/util.h> -#include <intelblocks/ebda.h> -#include <intelblocks/systemagent.h> -#include <stdlib.h> - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry fsp_mem; - struct range_entry tolum; - - /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - if (fsp_find_bootloader_tolum(&tolum)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); - - /* Locate the FSP reserved memory area */ - if (fsp_find_reserved_memory(&fsp_mem)) - die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - - cfg->tolum_end = range_entry_end(&tolum); - cfg->reserved_mem_size = range_entry_size(&fsp_mem); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_end; -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c index 6b0bd67..072023c 100644 --- a/src/soc/intel/common/block/ebda/ebda.c +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -17,34 +17,14 @@ #include <intelblocks/ebda.h> #include <string.h>
-/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ - -/* Fill up EBDA structure inside Mainboard directory */ -__weak void create_mainboard_ebda(struct ebda_config *cfg) -{ - /* no-op */ -} - -static void create_soc_ebda(struct ebda_config *cfg) -{ - /* Create EBDA header */ - cfg->signature = EBDA_SIGNATURE; - /* Fill up memory layout information */ - fill_soc_memmap_ebda(cfg); -} - -void fill_ebda_area(void) +void initialize_ebda_area(void) { struct ebda_config ebda_cfg;
/* Initialize EBDA area early during romstage. */ setup_default_ebda(); - create_soc_ebda(&ebda_cfg); - create_mainboard_ebda(&ebda_cfg); + ebda_cfg.signature = EBDA_SIGNATURE; + fill_memmap_ebda(&ebda_cfg); write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); }
diff --git a/src/soc/intel/common/block/include/intelblocks/ebda.h b/src/soc/intel/common/block/include/intelblocks/ebda.h index 16124df..1770e8f 100644 --- a/src/soc/intel/common/block/include/intelblocks/ebda.h +++ b/src/soc/intel/common/block/include/intelblocks/ebda.h @@ -16,52 +16,24 @@ #ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H #define SOC_INTEL_COMMON_BLOCK_EBDA_H
-#include <soc/ebda.h> - #define EBDA_SIGNATURE 0xebdaebda
-/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ +/* EBDA structure */ +struct ebda_config { + uint32_t signature; /* EBDA signature */ + uint32_t tolum_end; /* coreboot memory start */ + uint32_t reserved_mem_size; /* chipset reserved memory size */ +};
-/* Fill up EBDA structure inside Mainboard directory */ -void create_mainboard_ebda(struct ebda_config *cfg); +/* Initialize EBDA and store structure into EBDA area */ +void initialize_ebda_area(void);
/* - * SoC overrides - * - * All new SoC must implement below functionality for romstage. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg); - -/* - * API to perform below operation - * 1. Initialize EBDA area - * 2. Fill up EBDA structure inside SOC directory - * 3. Fill up EBDA structure inside Mainboard directory - * 4. Store EBDA structure into EBDA area - */ -void fill_ebda_area(void); - -/* Fill the ebda object pointed to by cfg. Object will be zero filled + * Fill the ebda object pointed to by cfg. Object will be zero filled * if signature check fails. */ void retrieve_ebda_object(struct ebda_config *cfg);
-/* - * EBDA structure - * - * SOC should implement EBDA structure as per need - * as below. - * - * Note: First 4 bytes should be reserved for signature as - * 0xEBDA - * - * struct ebda_config { - * uint32_t signature; - * <Required variables..> - * }; - */ +/* API for filling ebda with data */ +void fill_memmap_ebda(struct ebda_config *cfg);
#endif diff --git a/src/soc/intel/common/block/memmap/Kconfig b/src/soc/intel/common/block/memmap/Kconfig new file mode 100644 index 0000000..677400b --- /dev/null +++ b/src/soc/intel/common/block/memmap/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_MEMMAP + bool + select SOC_INTEL_COMMON_BLOCK_EBDA + help + Intel Processor common MEMMAP library support diff --git a/src/soc/intel/common/block/memmap/Makefile.inc b/src/soc/intel/common/block/memmap/Makefile.inc new file mode 100644 index 0000000..8da9815 --- /dev/null +++ b/src/soc/intel/common/block/memmap/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/common/block/memmap/memmap.c similarity index 96% rename from src/soc/intel/skylake/memmap.c rename to src/soc/intel/common/block/memmap/memmap.c index e98bf51..03ef3b8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/common/block/memmap/memmap.c @@ -46,7 +46,7 @@ }
/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) +void fill_memmap_ebda(struct ebda_config *cfg) { struct range_entry fsp_mem; struct range_entry tolum; @@ -65,8 +65,8 @@
void cbmem_top_init(void) { - /* Fill up EBDA area */ - fill_ebda_area(); + /* Initialize EBDA area */ + initialize_ebda_area(); }
/* diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 7ece9549..c8c4c24 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -20,6 +20,7 @@ select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_MEMMAP select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030..401b446 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c -bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += p2sb.c bootblock-y += uart.c @@ -26,7 +25,6 @@ romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -44,7 +42,6 @@ ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -62,7 +59,6 @@ smm-y += smihandler.c smm-y += uart.c
-postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c deleted file mode 100644 index 9c7f067..0000000 --- a/src/soc/intel/icelake/memmap.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <fsp/util.h> -#include <intelblocks/ebda.h> -#include <intelblocks/systemagent.h> -#include <stdlib.h> - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry fsp_mem; - struct range_entry tolum; - - /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - if (fsp_find_bootloader_tolum(&tolum)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); - - /* Locate the FSP reserved memory area */ - if (fsp_find_reserved_memory(&fsp_mem)) - die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - - cfg->tolum_end = range_entry_end(&tolum); - cfg->reserved_mem_size = range_entry_size(&fsp_mem); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_end; -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..dce1d6b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += memmap.c romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c @@ -55,7 +54,6 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -77,7 +75,6 @@ smm-y += uart.c smm-y += xhci.c
-postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c postcar-y += i2c.c