Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/1
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md new file mode 100644 index 0000000..3af893a --- /dev/null +++ b/Documentation/mainboard/ocp/deltalake.md @@ -0,0 +1,98 @@ +# OCP Delta Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Delta Lake server platform. + +## Introduction + +OCP Delta Lake server platform is a component of multi-host server system +Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. + +Delta Lake server is a one socket CooperLake Sacalable Processor server. + +Yosemite-V3 has multiple configurations. Depending on configurations, it may +host up to 4 Delta Lake servers in one sled. + +Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project. + +## Required blobs + +This board currently requires: +- FSP blob: The blob (Intel CooperLake Scalable Processor Firmware Support Package) + is not yet available to the public. It will be made public some time after the MP + of CooperLake Scalable Processor when the FSP is mature. +- Microcode: Not yet available to the public. +- ME binary: Not yet available to the public. + +## Payload +- Linuxboot: This is necessary only if you use Linuxboot as coreboot payload. + U-root as initramfs, is used in the joint development. It can be built + following [All about u-root]. + +## Flashing coreboot + +To do in-band FW image update, use [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +From OpenBMC, to update FW image: + fw-util slotx --update bios <path to coreboot image> + +To power off/on the host: + power-util slotx off + power-util slotx on + +To connect to console through SOL (Serial Over Lan): + sol-util slotx + +## Working features +The solution is developed using Linuxboot payload. The Linuxboot +kernel versions tried is 5.2.9. The initramfs image is u-root. +- Most SMBIOS types +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement +- SEL record generation +- Early serial output +- port 80h direct to GPIO +- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- Skipping memory training upon subsequent reboots +- BMC crash dump +- Error injection through ITP + +## Firmware configurations +[ChromeOS VPD] is used to store most of firmware configurations. RO_VPD +holds default values, while RW_VPD holds customized values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses its value to populate smbios type 1 version field. + +## Known issues / feature gaps +- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not + support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. +- VT-d is not supported. An IPS ticket is filed with Intel. +- PCIe bifuration is not supported. An IPS ticket is filed with Intel. +- SMBIOS type 7 and type 17 are not populated. +- ME based power capping. + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Intel CooperLake Scalable Processor | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 2500 | ++------------------------+---------------------------------------------+ +| PCH | Intel Lewisburg C621 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md