[coreboot-gerrit] Change in ...coreboot[master]: southbridge/intel/common/smbus.c: Add support for i2c block write

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30800 )

Change subject: southbridge/intel/common/smbus.c: Add support for i2c block write
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Patch Set 17:

(2 comments)

https://review.coreboot.org/#/c/30800/9/src/southbridge/intel/common/smbus.c 
File src/southbridge/intel/common/smbus.c:

https://review.coreboot.org/#/c/30800/9/src/southbridge/intel/common/smbus.c... 
PS9, Line 453: 	outb(cmd, smbus_base + SMBHSTDAT1);
> You mean a 16-bit address? but where is the lower part?

First byte of the block_cmd_loop() is the lower part.
In the I2C mode the controller sends out the value in SMBHSTDAT1, when a command is init.

https://review.coreboot.org/#/c/30800/17/src/southbridge/intel/common/smbus.... 
File src/southbridge/intel/common/smbus.c:

https://review.coreboot.org/#/c/30800/17/src/southbridge/intel/common/smbus.... 
PS17, Line 424: I801_BLOCK_DATA
> This is not the I2C command. I wonder now what is the difference […]

The do_smbus_block_write() does not check for i2c support and does not write the cmd to SMBHSTDAT1 register.