[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 )

Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
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Patch Set 6:

(2 comments)

File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/54959/comment/efabe451_1b3b656e 
PS6, Line 75: [PchSerialIoIndexGSPI0] = 1,
            : 		[PchSerialIoIndexGSPI1] = 1,
            : 		[PchSerialIoIndexGSPI2] = 1,
> You disable or hide the GSPI-Controllers but still enable their Chip Selct. […]

Yes I just checked, this is expected.

https://review.coreboot.org/c/coreboot/+/54959/comment/523ac94f_d6027737 
PS6, Line 87: [PchSerialIoIndexGSPI0] = 0,
            : 		[PchSerialIoIndexGSPI1] = 0,
            : 		[PchSerialIoIndexGSPI2] = 0,
> You set the chip select mode to "hardware mode" in SerialIoGSpiCsMode and then set the state to 0? T […]

Yes correct this is expected also.