[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36032 )

Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
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Patch Set 3: Code-Review-1

(1 comment)

https://review.coreboot.org/c/coreboot/+/36032/2/src/soc/intel/cannonlake/Kc... 
File src/soc/intel/cannonlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/36032/2/src/soc/intel/cannonlake/Kc... 
PS2, Line 128: 	  sum of FSP stack requirement (128KiB) and CB stack requirement (1KiB).
> @subrata/Kyosti, I think the description says that this is the stack usage in CAR which is used by b […]

@Patric: afaict VBOOT uses a heap defined by vboot_work in car.ld.

@V Sowmya: It should explicitly mention romstage stack usage as kyösti says, as the stack pointer is reinitialized at each stage. measuring bootblock/verstage stack usage has no meaning for romstage where FSP-M is called.