Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32175
Change subject: soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups ......................................................................
soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups
This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1.
BUG=b:121212459 TEST: Verified the GPIO MISCFG is getting set as per updated map.
Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32175/1
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 03f4314..cca2bc4 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -26,14 +26,14 @@ #define GPP_B 1 #define GPP_G 2 #define GROUP_SPI 3 -#define GPP_D 4 -#define GPP_F 5 -#define GPP_H 6 -#define GROUP_VGPIO 7 -#define GPD 9 -#define GROUP_AZA 0xA -#define GROUP_CPU 0xB -#define GPP_C 0xC +#define GPP_D 5 +#define GPP_F 6 +#define GPP_H 7 +#define GROUP_VGPIO 8 +#define GPD 0xA +#define GROUP_AZA 0xB +#define GROUP_CPU 0xC +#define GPP_C 4 #define GPP_E 0xD #define GROUP_JTAG 0xE #define GROUP_HVMOS 0xF