Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006
-gerrit
commit 70db0accbfa64201d93026419ee37d75c815eef8 Author: Stefan Reinauer reinauer@chromium.org Date: Fri Feb 14 13:41:39 2014 -0800
google/panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh shawnn@chromium.org Signed-off-by: Stefan Reinauer reinauer@chromium.org Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer reinauer@chromium.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Commit-Queue: Shawn Nematbakhsh shawnn@chromium.org Tested-by: Shawn Nematbakhsh shawnn@chromium.org Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer reinauer@chromium.org Tested-by: Stefan Reinauer reinauer@chromium.org --- src/mainboard/google/panther/acpi/platform.asl | 3 + src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++-------- 2 files changed, 71 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl index e6aaf75..1c70d49 100644 --- a/src/mainboard/google/panther/acpi/platform.asl +++ b/src/mainboard/google/panther/acpi/platform.asl @@ -68,5 +68,8 @@ Method(_PTS,1)
Method(_WAK,1) { + /* Initialize thermal defaults */ + _TZ.THRM._INI () + Return(Package(){0,0}) } diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index e0ea2f5..ddf4473 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -61,6 +61,14 @@ Scope (_TZ) Return (\PPKG ()) }
+ // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } + Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 @@ -170,14 +178,20 @@ Scope (_TZ) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (\F0PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (_STA ()) { + Store (1, \FLVL) + Store (\F1PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } }
@@ -191,14 +205,20 @@ Scope (_TZ) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (\F1PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (_STA ()) { + Store (2, \FLVL) + Store (\F2PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } }
@@ -212,14 +232,20 @@ Scope (_TZ) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (\F2PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (_STA ()) { + Store (3, \FLVL) + Store (\F3PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } }
@@ -233,14 +259,20 @@ Scope (_TZ) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (\F3PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } }
@@ -254,14 +286,20 @@ Scope (_TZ) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (\F4PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + _SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (_TZ.THRM, 0x81) + } } }