[coreboot-gerrit] Change in ...coreboot[master]: drivers/spi/sst.c: Add three remaining SST25*F080 chips

[mikeb mikeb (Code Review)]

Hello Mike Banon,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/30927

to review the following change.

Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips
......................................................................

drivers/spi/sst.c: Add three remaining SST25*F080 chips

Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.

Signed-off-by: Mike Banon 
Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b
---
M src/drivers/spi/sst.c
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30927/1

diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
index 559969a..63fae95 100644
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
@@ -78,6 +78,11 @@
    	.name = "SST25VF080B",
    	.ops = &spi_flash_ops_write_ai,
    },{
+		.idcode1 = 0x80,
+		.nr_sectors = 256,
+		.name = "SST25VF080",
+		.ops = &spi_flash_ops_write_ai,
+	},{
    	.idcode1 = 0x41,
    	.nr_sectors = 512,
    	.name = "SST25VF016B",
@@ -112,6 +117,16 @@
    	.nr_sectors = 128,
    	.name = "SST25WF040",
    	.ops = &spi_flash_ops_write_ai,
+	},{
+		.idcode1 = 0x05,
+		.nr_sectors = 256,
+		.name = "SST25WF080",
+		.ops = &spi_flash_ops_write_ai,
+	},{
+		.idcode1 = 0x14,
+		.nr_sectors = 256,
+		.name = "SST25WF080B",
+		.ops = &spi_flash_ops_write_ai,
    },
 };