Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48847 )
Change subject: soc/intel/alderlake: Update CPU microcode patch base address/size
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Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48847/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/48847/1//COMMIT_MSG@9
PS1, Line 9: This patch updates CPU microcode patch base address/size to FSP-S
: UPD to have second microcode patch loaded successfully to enable
: Mcheck flow
At what point in the boot sequence is this expected? Why can't coreboot do this instead of relying o […]
Are we potentially missing this from TGL as well? We have rarely, if ever, used the FSP's ucode loading facility in the past, coreboot typically handles the "2nd microcode load" (apart from the FIT load)
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