[coreboot-gerrit] Change in coreboot[master]: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40838 )

Change subject: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/graphics.c
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40838/1

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index a3f38c2..eaac177 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -51,22 +51,21 @@
 static void soc_config_pwrmbase(void)
 {
    uint32_t reg32;
+	uint16_t reg16;

/*
     * Assign Resources to PWRMBASE
     * Clear BIT 1-2  Command Register
     */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);

/* Program PWRM Base */
    pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);

/* Enable Bus Master and MMIO Space */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MEMORY;
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);

/* Enable PWRM in PMC */
    reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c
index eaa07c3..96b1ca8 100644
--- a/src/soc/intel/tigerlake/graphics.c
+++ b/src/soc/intel/tigerlake/graphics.c
@@ -49,9 +49,9 @@
    	return;

/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config16(dev, PCI_COMMAND, reg16);

/* Initialize PCI device, load/execute BIOS Option ROM */
    pci_dev_init(dev);