build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35348 )
Change subject: Rangeley: Fix incorrect BCLK ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35348/2/src/cpu/intel/fsp_model_406... File src/cpu/intel/fsp_model_406dx/acpi.c:
https://review.coreboot.org/c/coreboot/+/35348/2/src/cpu/intel/fsp_model_406... PS2, Line 175: printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n", trailing whitespace
https://review.coreboot.org/c/coreboot/+/35348/2/src/cpu/intel/fsp_model_406... PS2, Line 175: printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n", space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35348/2/src/cpu/intel/fsp_model_406... PS2, Line 180: printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", trailing whitespace