[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Don't add MC resource twice

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47173 )

Change subject: soc/intel/xeon_sp: Don't add MC resource twice
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Patch Set 1:

How does this actually work? Do both memory controllers have the
same memory map set up? Do they align somehow on things like TSEG,
or does each have its own TSEG relative to its own DRAM?