[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/brya0: Fix irq and CS lines for FPMCU

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Tim Wawrzynczak, EricR Lai.
Hello build bot (Jenkins), Furquan Shaikh, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55147

to look at the new patch set (#2).

Change subject: mb/google/brya/brya0: Fix irq and CS lines for FPMCU
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mb/google/brya/brya0: Fix irq and CS lines for FPMCU

The entries in the ACPI tables for the fingerprint module's SPI
configuration were incorrect.

1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be
   described by Interrupt(), not GpioInt()
2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on`

BUG=b:181635081
TEST=verified in kernel logs:
localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi'
[    4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected
[    4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered

Signed-off-by: Tim Wawrzynczak 
Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55147/2