[coreboot-gerrit] Change in coreboot[master]: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge

[Werner Zeh (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36671

to look at the new patch set (#2).

Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
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mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge

On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.

Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36671/2