Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45056 )
Change subject: soc/amd/picasso: Add MADT entry for GNB IOAPIC ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45056/6/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45056/6/src/soc/amd/picasso/acpi.c@... PS6, Line 50: FSP populates this generates this HOB if it initializes second IOAPIC
I'd be fine with passing the address in and forcing FSP to obey the UPD. In that case, I'd probably take FSP's default back to disabled and make coreboot enable it intentionally.
I think that would be fine. Just selecting an address and providing it to FSP will allow us to control the placement in coreboot.
Hmm, I thought we were already reserving a big chunk of space that should've covered it.
I don't think that's true. From coreboot logs, I see that 0x1000 bytes at IO_APIC_ADDR are marked as reserved: ``` update_constraints: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) ```
And the space following that is available for MMIO allocation: ``` * Base: fec01000, Size: f000, Tag: 200 ```
So, depending upon what address is chosen we will have to update the reservations accordingly.
You wouldn't put it in picasso/root_complex.c?
Right now the IO_APIC_ADDR reservation is marked as part of lpc.c. But I see your point about root_complex.c since this IOAPIC is the one in NB. So, root_complex.c should be fine.