[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake/include: Include headers from soc/intel/icelake

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36551 )

Change subject: soc/intel/tigerlake/include: Include headers from soc/intel/icelake
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/ramstage.h:

https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... 
PS1, Line 24: void mainboard_silicon_init_params(FSP_S_CONFIG *params);
need consistent spacing around '*' (ctx:WxV)

https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/romstage.h:

https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... 
PS1, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)