Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42860 )
Change subject: mb/google/octopus/variants/dood: fix disable_xhci_lfps_pm by sku ......................................................................
mb/google/octopus/variants/dood: fix disable_xhci_lfps_pm by sku
due to overridetree.cb set disable_xhci_lfps_pm = 0, need correct condition expression to let function work.
BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan kenneth.chan@quanta.corp-partner.google.com Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff --- M src/mainboard/google/octopus/variants/dood/variant.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42860/1
diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 21e52f7..dda24f8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -68,7 +68,7 @@
cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
- if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { switch (google_chromeec_get_board_sku()) { case SKU_1_LTE: case SKU_3_LTE_2CAM: