Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(6 comments)
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/9f759562_8891a71d PS6, Line 33: 0x11a
Oops, well-spotted.
Done
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/10d2b3c7_37128a5d PS6, Line 62: slotcap |= func << 19;
BIOS spec says this should be unique. In case MRC does something […]
For now, I've initialised the port number using `func + 1`, which matches what vendor firmware does. I've added devicetree options, in case someone wants to adjust this.
Oh, and I need to update the Slot Implemented bit for onboard devices. Reference code always sets this bit, but apparently it's R/WO.
https://review.coreboot.org/c/coreboot/+/47223/comment/dd2b2e73_b976c6e8 PS6, Line 68: /* 75 watts power limit */
Devicetree, probably. i945 also has a FIXME.
Reference code hardcodes 75 W. I've added devicetree options in case someone wants to override this, but I doubt anyone will use them.
https://review.coreboot.org/c/coreboot/+/47223/comment/8160845f_b96a9589 PS6, Line 69: 0x3ff
`0xff` (the rest is already set above)
Done
https://review.coreboot.org/c/coreboot/+/47223/comment/98f3ccb1_540f7c1a PS6, Line 75: or
No need to read, just pci_write_config16() would do.
Done
https://review.coreboot.org/c/coreboot/+/47223/comment/4bd0c6d0_97a367d1 PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
Nothing new. Anyway, if you are sure that other code forces it to 1, that's […]
Interesting. Vendor firmware on a Toshiba Satellite Pro L70-A enables OBFF. I'll leave this as-is.